As the design density of integrated circuits increases, and design features get smaller, there is a need for higher switching speeds in transistors.
In un-strained silicon, the lowest energy level in the conduction band has six discrete electron states. Each state has a different momentum value, and only a small input of energy is required for an electron to move from one state to another. When the lattice is under tensile strain, its physical symmetry is broken, and with that the electronic symmetry. The lowest energy level of the conduction band is split, with two of the six original states dropping to a lower energy level and four rising to a higher energy level. Thus, it becomes more difficult for the electrons to be ‘scattered’ between the lowest energy states by a phonon, because there are only two states to occupy.
When electrons scatter, their motion is randomized. Reducing scatter increases the average distance an electron can travel before it is knocked off course, thus increasing its average velocity in the conduction direction. Also, distorting the lattice through tensile strain can distort the electron-lattice interaction in a way that reduces an electron's effective mass. An electron's effective mass governs its acceleration in an applied electric field.
The application of stress lifts the degeneracy between light and heavy-hole bands. In addition, the spin-orbit band is lowered in energy with respect to the other two bands. Due to this, the interband and intraband scatterings are reduced, which results in a significant improvement in hole mobility. Both tensile and compressive strain increase hole mobility compared to unstrained silicon, but the increase is lower for a tensile strain. This is because of the bigger intraband scattering rate for tensile strain. This higher scattering rate in the tensile situation can be understood considering that the density of states in the heavy hole band in the tensile case is larger than in the compressive case. J. E. Dijkstra et al., Journal of Applied Physics, vol 81, 1259 (1997); D. K. Nayak et al., Applied Physics Letters, vol 64, 6663 (2000).
U.S. Pat. No. 6,573,172, issued Jun. 3, 2003, to En et al., teaches forming a PECVD silicon nitride layer having a compressive stress on the gate electrode region and the source/drain regions to impart a tensile stress in an underlying channel of a NMOS transistor.
In the case of a PMOS device, the hole mobility of strained silicon (Si) has been shown to have higher mobility compared to that of unstrained Si. U.S. Pat. No. 6,621,131, issued Sep. 16, 2003, to Murthy et al., teaches depositing source and drain films containing an alloy of silicon and germanium. The inclusion of germanium results in compressive stress in a channel of a PMOS transistor. U.S. Pat. No. 6,046,494, issued Apr. 4, 2000, to Brigham et al., teaches formation of a conformal blanket silicon nitride layer on the silicide layer of a PMOS transistor. Brigham et al. teach that the residual tensile stress of the conformal silicon nitride layer results in a compressive stress being applied to the layers below the nitride layer, resulting in improved interfacial characteristics at the oxide—silicon interface. U.S. Pat. No. 6,573,172, issued Jun. 3, 2003, to En et al., teaches forming a conformal PECVD silicon nitride layer having a tensile stress on the gate electrode region and the source/drain regions to impart a compressive stress in an underlying channel of a PMOS transistor.
There is a need for methods and structures to increase compressive strain in the channel region of a PMOS transistor and thereby to promote higher hole mobilities, which increase transistor drain current and device performance.